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(parent: 83ffe59) | patch
lantiq: Fixed reading the number of RX FIFOs in the SPI driver
authorblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 19 Oct 2015 10:08:18 +0000 (10:08 +0000)
committerblogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Mon, 19 Oct 2015 10:08:18 +0000 (10:08 +0000)
commit249c4c58e4f448321348b447f3acdbf9c2feaef3
treebfb0223d378b3800b0822ce1fea583f10740cfd2tree | snapshot
parent83ffe595f9f9ea577224a3dbacdf8e587de78bc9commit | diff
lantiq: Fixed reading the number of RX FIFOs in the SPI driver

Until now the SPI driver used the TX bits for the RX FIFO. This seems
uncritical for now since both are equals on my devices (VR9), but this
could cause problems on other SoCs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47208 3c298f89-4303-0410-b956-a3cf2f4a3e73
target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch diff | blob | history
target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch diff | blob | history
OpenWrt main development branch