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(parent: 7ee23fa) | patch
[ramips] uart_clk on Rt3352F is always 40MHz
authorJohn Crispin <blogic@openwrt.org>
Tue, 24 Jul 2012 20:37:50 +0000 (20:37 +0000)
committerJohn Crispin <blogic@openwrt.org>
Tue, 24 Jul 2012 20:37:50 +0000 (20:37 +0000)
commit664e8551c66ac46c26111942138d7d5bbffedd03
tree0c5f16afaac5b361c18502777986bb81167f234etree | snapshot
parent7ee23fa260ad597e82771fdeed25642260ff4650commit | diff
[ramips] uart_clk on Rt3352F is always 40MHz

Currently, sys_clk/10 is used which is just wrong.
cpu_clk/10 would work for systems with 400MHz CPU clock.

Signed-off-by: Daniel Golle <dgolle@allnet.de>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32812 3c298f89-4303-0410-b956-a3cf2f4a3e73
target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c diff | blob | history
OpenWrt 15.05 release branch