MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup);
 
-
-static void __init om2p_hs_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-              AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE |
-              AR934X_ETH_CFG_SW_PHY_SWAP);
-
-       t |= AR934X_ETH_CFG_SW_PHY_SWAP;
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init om2p_hs_setup(void)
 {
        u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
 
        ath79_register_wmac(art, NULL);
 
-       om2p_hs_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
        ath79_register_mdio(1, 0x0);
 
        ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
 
        },
 };
 
-static void __init rb2011_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-               AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
-       t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
-
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init rb2011_wlan_init(void)
 {
        u8 *hard_cfg = (u8 *) KSEG1ADDR(0x1f000000 + RB_HARD_CFG_OFFSET);
        ath79_register_m25p80(&rb2011_spi_flash_data);
        rb2011_nand_init();
 
-       rb2011_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
+                                  AR934X_ETH_CFG_SW_ONLY_MODE);
 
        ath79_register_mdio(1, 0x0);
        ath79_register_mdio(0, 0x0);
 
        },
 };
 
-static void __init wdr4300_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-              AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
-       t |= AR934X_ETH_CFG_RGMII_GMAC0;
-
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init wdr4300_setup(void)
 {
        u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
        ap9x_pci_setup_wmac_led_pin(0, 0);
        ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac);
 
-       wdr4300_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
 
        mdiobus_register_board_info(wdr4300_mdio0_info,
                                    ARRAY_SIZE(wdr4300_mdio0_info));
 
        },
 };
 
-static void __init db120_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-              AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
-       t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
-
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init tl_wr1041nv2_setup(void)
 {
        u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
                                         tl_wr1041nv2_gpio_keys);
        ath79_register_wmac(ee, mac);
 
-       db120_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
+                                  AR934X_ETH_CFG_SW_ONLY_MODE);
 
        ath79_register_mdio(1, 0x0);
        ath79_register_mdio(0, 0x0);
 
        }
 };
 
-static void __init tl_wr841n_v8_gmac_setup(void)
-{
-       void __iomem *base;
-       u32 t;
-
-       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
-
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
-       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-              AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE |
-              AR934X_ETH_CFG_SW_PHY_SWAP);
-
-       t |= AR934X_ETH_CFG_SW_PHY_SWAP;
-       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
-       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
-
-       iounmap(base);
-}
-
 static void __init tl_wr841n_v8_setup(void)
 {
        u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
 
        ath79_register_m25p80(&tl_wr841n_v8_flash_data);
 
-       tl_wr841n_v8_gmac_setup();
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
 
        ath79_register_mdio(1, 0x0);